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Recall Part1 & Part2 Contents
Disclaimer
Pre-requisites
Intro and Course contents
Course WA group Link
K-map to Circuit
Platform Overview
Day1_SOPvsPOS_Kmap_LogicOptimization
KMap with Multiplexer 1
Kmap with multiplexer verilog implementation
Kmap with multiplexer Verification
Sequential Circuit
Latches and Flip-Flops
D flipFlop_1
D fliFlop_2_synchronousVsAsynchronousReset
D flipFlop_reset_to_different_value
D fliFlop with Bit enable
D Latch
DFF with Gate
Mux and DFF
Create Circuit from Truth Table (JK_FF)
Detect an edge
Detect both edges
Edge capture register
Dual-edge triggered flip-flop
Counters
Four Bit BInary Counter
Recall Counter Hardware implementation
Decade Counter
Slow Decade Counter
Counter 1000 (frequency Division)
4-digit Decimal Counter
12-hour clock
Shift Register
4-bit shift Register
right_left rotator (shift register)
Left_right Airthnatic Shift
Lfsr5
32 bit Lfsr
Shift Register(DEMUX)
3_input_LUT
We Apologize For The Delay in Upload, VIDEO UPLOAD RESUMED
FSM problems
Pre-requisite
fsm_1_2
Simple FSM2
simple FSM2 Alternative way
Simple state transitions 3
Simple one-hot state transition 3
Design a Moore FSM
DEsign a Moore FSM (REVISIT)
Lemmings1
Lemmings2
Lemmings3
lemmings4
Fsm onehot
Fsm ps2
Fsm ps2data
Serial reciever
Serial reciever and data path
Sequence Recognition
Design a Mealy FSM
Serial 2sCompliment(Moore)
Serial 2sCompliment(Mealy)
Self Study Problems
Another FSM
Building larger Circuit
MInor_porject0_intro
Data path vs control path
Mino_project0_part1
Minor_project0_part2
Minor_project0_part3
Minor_project0_part4
Minor_project0_part5
HandsOn Verification
Finding Bugs in Code
Mux
NAND
Mux_1
Add_Sub
Case statement
Building Circuit from simulation waveforms
comb_Ckt_1_4
Comb_ckt_5_6
Sequencial_ckt_7
Sequential_ckt_8
Sequential_ckt_9
Writing TestBench
Clock
Tb_1
And gate
T_Flip_flop
MinorProjects 1
P1_Motivation of why
P2_Algorithm
P3_Hardware needed
P4_Develop Schematics
P5_verilog_coding_strategy
EDA_playground Overview
P6_Verilog Code of Data Path
P7_Control_path_state_transition
P8_Verilog Code of Control Path
P9_TestBench and Simulation
Extras (Project Ideas ,Interview Questions)
Get Certificate
To earn certificate you must score more than 75% in quiz , more than 75% completed course work, Optional : Upload at least one minor projcet in gitHub and share in linkedIN
STEP1 (Optional): Share LinkedIN post link , which have github repo link
STEP2: Quiz have only 1 correct answer and few question has negative marks for a wrong answer
Quiz_L1